OpenSPARC T1 Download for the Chip Design and Verification includes:

• Chip Design source code in Verilog language.
• Verification test benches source code in Verilog, Vera®, PLI code in C and C++.
• Verification tests source code in SPARC assembly language.
• Scripts needed to assemble and run tests on the design using verification test benches.
• Synthesis scripts for Synopsys Design Compiler®.
• SPARC Architecture Simulator (SAS).
• Documentation.

OpenSPARC T1 Download for Architecture and Performance modeling includes:

• SAM - SPARC Architecture Model
• Legion - Fast instruction accurate simulator for software developers
• SPARC Architecture Simulator (SAS).
• Solaris image for simulation.
• Documentation.