Once you download the source code, to run simulations of the OpenSPARC T1 you will need the following:

• A Verilog Simulator - VCS® from Synopsys or NC-Verilog® from Cadence or Rivera® from Aldec (see their 90 day free evaluation)
  
• Optionally, Vera® compiler and run time libraries from Synopsys.
• Optionally, Debussy® debug system from Novas for simulation debugging.

To run Synthesis of OpenSPARC T1, you will need:

• Design Compiler® from Synopsys.
• Your silicon fab vendor's synthesis libraries.

To run FPFGA Synthesis of OpenSPARC T1, you will need:

• Synplify Pro® from Synplicity.