What are the differences between OpenSPARC T1 and UltraSPARC T1?

OpenSPARC T1 source code is modified from the original source code of UltraSPARC T1. Every attempt is made to keep the OpenSPARC T1 source as close to the original UltraSPARC T1 in the process of preparing it for release in a standalone environment and preparing it to comply with the legal requirements.

What is included in the OpenSPARC T1 download?

OpenSPARC T1 Download for the Chip Design and Verification includes:

• Chip Design source code in Verilog language.
• Verification test benches source code in Verilog, Vera®, PLI code in C and C++.
• Verification tests source code in SPARC assembly language.
• Scripts needed to assemble and run tests on the design using verification test benches.
• Synthesis scripts for Synopsys Design Compiler®.
• SPARC Architecture Simulator (SAS).
• Documentation.

OpenSPARC T1 Download for Architecture and Performance modeling includes:

• SAM - SPARC Architecture Model
• Legion - Fast instruction accurate simulator for software developers
• SPARC Architecture Simulator (SAS).
• Solaris image for simulation.
• Documentation.

What are the system requirements to use OpenSPARC T1 source code?

Once you download the source code, you can run Verilog simulation, RTL synthesis, Architecture and Performance modeling tools on any SPARC system with Solaris 9 or Solaris 10 operating system.

What are the commercial EDA tools needed to use the OpenSPARC T1 source code?

Once you download the source code, to run simulations of the OpenSPARC T1 you will need the following:

• A Verilog Simulator - VCS® from Synopsys or NC-Verilog® from Cadence or Rivera® from Aldec (see their 90 day free evaluation)
  
• Optionally, Vera® compiler and run time libraries from Synopsys.
• Optionally, Debussy® debug system from Novas for simulation debugging.

To run Synthesis of OpenSPARC T1, you will need:

• Design Compiler® from Synopsys.
• Your silicon fab vendor\'s synthesis libraries.

To run FPFGA Synthesis of OpenSPARC T1, you will need:

• Synplify Pro® from Synplicity.

Can I use Verilog simulator other than VCS or NC-Verilog ?

Yes, you can use any Verilog Simulator, but please make sure to follow instructions to compile and link PLI C/C++ code, and specify correct parameters to the Simulation script.

• Design Compiler®, VCS®, Vera® are registered trademarks of Synopsys, Inc.
• NC-Verilog® is registered trademark of Cadence, Inc.
• Debussy® is registered trademark of Novas, Inc.