EPHAM 2008
Workshop on Exploiting Parallelism with Transactional
Memory
and other Hardware Assisted Methods
http://www.opensparc.net/conf/epham2008/
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Held with
April 6 - 9, 2008
Boston, Massachusetts |
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Welcome to the website for the 2008 Workshop on Exploiting Parallelism
using Hardware Assisted Methods. EPHAM 2008 will be held in conjuction
with the the 2008 International Symposium on Code Generation and
Optimization (CGO 2008) on April 6, 2008 in Omni Parker House Hotel,
60 School Street, Boston, Massachusetts. The workship will provide a
forum for compiler and processor architecture researchers to exchange
ideas for leveraging hardware assistance to break down traditional
barriers to exploiting parallelism.
This first workshop will focus on compilation techniques for exploiting
parallelism in emerging multi-core and multi-threaded architectures
with a particular focus on the use of transactional memory to overcome
traditional barriers to parallelization. Current trends in
micro-processor architecture clearly point to a tapering off of clock
frequencies, and a shift toward supporting many cores and threads.
This change makes the compiler's task of extracting and exploiting
parallelism in applications even more important. Recognizing various
difficulties in parallelization, implementations are emerging that
attempt to provide various forms of hardware assist for the same. One
of these techniques, transactional memory, has recently drawn
significant interest in both industry and academia. Transactional
memory will be a focus, but other techniques to solve this problem are
also of interest.
The following are examples of topics for contributions to the
workshop. The list is not exhaustive, and is intended only as a
guideline. Any suitable contribution pertaining to the main theme
will be given full consideration.
- Novel optimizations using transactional memory
- Speculative parallelization and other speculative methods
- Ideas for implementing transactional memory in hardware or software
- Hybrid techniques for designing and using transactional memory
- Language constructs to enable programming with transactional memory
- Run-time techniques to overcome memory aliasing using transactional memory
- New ideas for transaction failure control and avoidance
- Debugging programs that exploit transactional memory
- Performance analysis and tools related to transactional parallelization
- Other hardware-assisted methods for extracting and exploiting parallelism
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Sunday, 6 April 2008
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8:00 - 8:10
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Opening Remarks
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8:10 - 8:35
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Hardware Acceleration for Lock-Free
Data Structures and Software-Transactional
Memory
Stephan Diestelhorst (Technische Universität
Dresden, Germany),
Michael Hohmuth (AMD)
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8:35 - 9:00
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Towards Fair Scalable Locking
Enrique Vallejo (University of Cantabria, Spain),
Sutirtha Sanyal (Barcelona Supercomputing Centre,
Spain),
Tim Harris (Microsoft Research Cambridge, UK),
Fernando Vallejo (University of Cantabria, Spain),
Ramón Beivide (University of Cantabria,
Spain),
Osman Unsal (Barcelona Supercomputing Centre,
Spain),
Adrián Cristal (Barcelona Supercomputing Centre,
Spain),
Mateo Valero (Barcelona Supercomputing Centre, Spain)
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9:00 - 9:25
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Energy Implications of Transactional Memory for
Embedded Architectures
Cesare Ferri (Brown University),
Amber Viescas (Swarthmore College),
Tali Moreshet (Swarthmore College),
Iris Bahar (Brown University),
Maurice Herlihy (Brown University)
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9:25 - 9:50
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Runtime Tuning of STM Validation Techniques
Rui Zhang (Rice University),
Zoran Budimlić (Rice University),
William N. Scherer III (Rice University),
Mackale Joyner (Rice University)
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9:50 - 10:15
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Break
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10:15 - 10:40
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Transactional Runtime Extensions for Dynamic
Language Performance
Nicholas Riley (UIUC),
Craig Zilles (UIUC)
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10:40 - 11:05
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Extending Contention Managers for User-Defined
Priority-Based Transactions
Justin Gottschlich (University of Colorado),
Daniel A. Connors (University of Colorado)
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11:05 - 11:55
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Industry Views on Transactional Memory
Industry researchers will present their views
on TM - outlook, major issues, what the
community could/should do to accelerate
adoption etc.
Ali-Reza Adl-Tabatabai (Intel),
Trey Cain (IBM),
David Christie (AMD),
Dan Nussbaum (Sun)
Discussion/Q&A: All
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11:55 - 12:00
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Closing Remarks
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| Extended abstract due: |
Monday, January 28, 2008 |
| Acceptance Notification: |
Monday, February 18, 2008 |
| Final version due: |
Monday, March 3, 2008 |
| General Chair: |
Partha Tirumalai (Sun) |
| Program Chair: |
Yonghong Song (Sun) |
| Publication Chair: |
Spiros Kalogeropulos (Sun) |
| Program Committee: |
Ali-Reza Adl-Tabatabai (Intel)
David Christie (AMD)
Rudolf Eigenmann (Purdue)
Vinod Grover (nVIDIA)
Tim Harris (Microsoft)
Maged Michael (IBM)
Mark Moir (Sun)
Ravi Rajwar (Intel)
Lawrence Rauchwerger (Texas A&M)
Mike Schlansker (HP)
Pen-Chung Yew (Univ. of Minnesota)
Craig Zilles (UIUC)
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Extended abstracts of 6-10 pages may be submitted using any format.
The abstract should clearly state the problem being studied, the
methods used, and the results. If the results are preliminary, the
authors should state their expectation for the final results. The
workshop is meant to be a forum encouraging open exchange of ideas
among researchers. As such, authors will retain the copyright for
their submissions. A primary goal is to foster collaboration between
academic and industry researchers. Promising but not yet fully
studied ideas will be given due consideration. To submit, please
e-mail a pdf of your submission to epham@acm.org.
Final submissions should use the standard ACM conference format (two
columns with 9 pt Times Roman font, etc.). Please use the Latex and
Word templates from ACM's proceedings page:
http://www.acm.org/sigs/pubs/proceed/template.html
All final submissions should be in pdf and should be printable on
8.5" x 11" US Letter size paper.
For further information, please send e-mail to epham@acm.org.