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Tuesday, 17 April 2007 04:33 |
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Ashu Sharma is a Graduate Intern at Sun Microsystems,
working on the OpenSPARC project. He graduated from UC Santa Cruz with a
BS in Computer Engineering with a passion for Computer Architecture. He joined the OpenSPARC group because he saw enormous potential for this
project and wanted to gain experience and learn things that he otherwise
would not have in a traditional classroom. He loves how the OpenSPARC
community has come together to participate in this unique initiative
to further processor architecture development and encourage innovation
and new ideas. He says, "Keep it up everyone!".
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Friday, 14 December 2007 07:00 |
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Dr. Alexandra Fedorova heads the systems research group at the School of
Computing Science at Simon Fraser University. She has obtained her Ph.D.
in Computer Science at Harvard University, where she worked on operating
system scheduling for multicore and multithreaded processors. During her
Ph.D. program, Fedorova also worked at Sun Microsystems labs, where she
conducted research on operating system design for multicore processors and
on transactional memory. Fedorova is a lead inventor on nine US patent
applications. Her current research focuses on operating system design for
many-core processors.
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Tuesday, 23 May 2006 05:40 |
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Keith Bierman has been supporting the OpenSPARC team with his humor and vast bits and bytes of knowledge since November 2005.
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Friday, 29 September 2006 08:03 |
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Nathan Brookwood has been an active participant
in the information technology industry since the days of the first
transistorized computers, Nathan has worked for and with suppliers of
mainframes, minicomputers, personal computers and semiconductors.
Some associates recall observations that date from Nathans
Insight 12 activities as a PDP-8 systems programmer. His
responsibilities have included hardware and software development, as
well as product and strategic marketing. He launched a variety of
hardware, software, communications and chip-level products. He has
analyzed and commented on the industry from perches at both D.H.
Brown Associates and Gartner/Dataquest.
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Tuesday, 17 April 2007 04:34 |
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Durgam Vahia is currently leading OpenSPARC Engineering teams at Sun.
In his prior roles, Durgam has led and contributed in various projects
in the areas of VLSI CAD tools development, logic design and microprocessor
verification. Durgam has keen interest in enabling multi-core research
in academic institutions throughout the world, by providing out-of-the-box
and reconfigurable open-source hardware platforms, and believes OpenSPARC
is key in making that happen.
Durgam received his MS in Computer Engineering from University of
Massachusetts at Amherst and was a co-recipient of Sun's Chairman's Award
for Innovation in 2004 for his work on memory consistency
model verification.
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Tuesday, 17 April 2007 04:28 |
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Dr. Ismet Bayraktaroglu has joined Sun Microsystems in December 2001
as a member of the technical staff. Since then he has worked on
development of a vera based verification flow for microprocessor
testability features, development of a memory bist ip, and development
of an at speed ATPG based functional datapath test methodology.
Dr. Bayraktaroglu has a BS and MS in electrical engineering from
Bogazici University, Istanbul, Turkey, and a PhD in computer
engineering from the University of California, San Diego. His
research interests include design for test, BIST, diagnosis of
BIST designs, test pattern compression, and concurrent test of DSPs.
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Tuesday, 18 September 2007 07:19 |
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Jared Smolens is a PhD candidate in the Electrical and Computer Engineering Department at Carnegie Mellon University. He has been using the OpenSPARC since its initial public release. He is responsible for the Transplant community project, which allows complete operating systems and user applications to execute on the OpenSPARC RTL model. At CMU, his thesis work is focused on designing light-weight detection of soft errors and device wearout in microprocessors. His research interests include multiprocessor and microprocessor architecture, reliability, and performance modeling.
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Tuesday, 23 May 2006 05:47 |
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Aman Joshi has been involved with Niagara project the very day he joined Sun, in 2002, to help integrate the Afara team. His involvement has been from the EDA/CAD tools side. For him it has been a wonderful team to work with since everyone is so focused on quality & delivering results - like a "start up" within the company.
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Tuesday, 23 May 2006 06:18 |
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Poonacha Kongetira is the Director of the Niagara Processors group. He's been part of the Niagara CPU design team from the early 'whiteboard' design stage at Afara Websystems, through the tapeout and eventual productization of Niagara at Sun Microsystems.
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Tuesday, 17 April 2007 04:31 |
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Kushal Datta is a doctoral student in University of North Carolina at
Charlotte and working as a Graduate Student Intern in the OpenSPARC T1
FPGA Engineering Group. His major area of interest encompasses
architecture exploration of multiprocessor system-on-chip's on network
of FPGAs, parallel architectures, multi-core Soc's and high performance
computing. He is also interested in Massive Parallel Computing Systems
and is an active member in Reconfigurable Computing Systems Lab in UNCC.
He is responsible for interfacing T1 core with the Xilinx Microblaze
processor on FPGA to enhance compatibility of the T1 core with the
kernel of a commercial OS.
He is also contributing to map a dual core multi-threading T1 on FPGA
(fun stuff!).
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Friday, 15 September 2006 08:00 |
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Dwayne Lee has been involved with the OpenSPARC project since just before it was launched. He was the one responsible for getting the web infrastructure and content in place. Part of his time is also spent as the OpenSPARC Community Manager.
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Tuesday, 23 May 2006 06:20 |
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Shrenik Mehta is the Director of Frontend Technologies and OpenSPARC program. As Director for Frontend Technologies he is responsible for the tools and methodology in the areas of Simulation/Hardware Acceleration, Formal Verification, Testability & Debug tools, Implementation and Verification IP used in the development and validation of ASICs, Processors and Systems.
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