Dwayne Lee: Niagara 2 @ Fall Microprocessor Forum 2006

Written by Dwayne Lee

Thursday, 12 October 2006 02:58

Robert Golla, one of the principal architects on Niagara 2, give a presentation at the Fall Microprocessor Forum 2006 this past week, October 9-11. A few more details of the design were presented including:
Robert Golla, one of the principal architects on Niagara 2, give a presentation at the Fall Microprocessor Forum 2006 this past week, October 9-11. A few more details of the design were presented including:

Niagara2 has improved performance vs. UltraSparc T1

Better integer throughput and throughput/watt (>2x)
Improved integer single-thread performance (>1.4x)
Better floating-point throughput (>10x)
Better floating-point single-thread performance (>5x)

The presentations is posted at OpenSPARC.net.

A few articles have been written too:

Sun, Fujitsu promise Sparc speed surge by Stephan Shankland (CNet)
Fall Processor Forum: Niagara, Act Two by Craig Morris (Heise)
Chip Makers to Outline Road Maps by Jeffery Burt (eWeek)

All very exciting and 2007 is looking to be a great year.

[ T: OpenSPARC ]

Read original article at: http://blogs.sun.com/dwaynelee/entry/niagara_2_fall_microprocessor_forum.